4 years ago

Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS.

David Leon Pohl, Jens Janssen, Tomasz Hemperek, Michael Daas, Hans Krüger, Marco Vogt

The RD53 collaboration is currently designing a large scale prototype pixel readout chip in a 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

Publisher URL: http://arxiv.org/abs/1711.03212

DOI: arXiv:1711.03212v1

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